#ifndef __SIS7019_H
#define __SIS7019_H 


/* PCI vendor and device ID */
#ifndef PCI_VENDOR_ID_sis7019
#define PCI_VENDOR_ID_sis7019		0x1023
#endif

#ifndef PCI_VENDOR_ID_SI
#define PCI_VENDOR_ID_SI			0x1039
#endif

#ifndef PCI_DEVICE_ID_SI_7018
#define PCI_DEVICE_ID_SI_7018		0x7018
#endif

#ifndef PCI_DEVICE_ID_SI_7019
#define PCI_DEVICE_ID_SI_7019		0x7019
#endif

#ifndef FALSE
#define FALSE 		0
#define TRUE  		1
#endif

#define CHANNEL_REGS	5
#define CHANNEL_START	0xe0   // The first bytes of the contiguous register space.

#define BANK_A 		0
#define BANK_B 		1
#define NR_BANKS		2

#define sis7019_FMT_STEREO     0x01
#define sis7019_FMT_16BIT      0x02
#define sis7019_FMT_MASK       0x03

//smliu for AC3
#define SIS_FMT_AC3      0x04

#define DAC_RUNNING	0x01
#define ADC_RUNNING	0x02

/* Register Addresses */

#define SIS7019_SPDIF_CS	0x70
#define SIS7019_GC_CIR		0xa0
#define SIS7019_ADDRESS_INT_UPDATE		0x01
#define SIS7019_SPDIF_OUT_NON_PCM		2
enum sis_ac97_registers {
	SIS_AC97_WRITE       = 0x40, SIS_AC97_READ = 0x44
};

/* Bit mask for operational registers */
#define AC97_REG_ADDR      0x000000ff

enum sis_ac97_bits {
	SIS_AC97_WRITE_ACTION = 0x8000, SIS_AC97_READ_ACTION = 0x8000,
	SIS_AC97_AUDIO_BUSY = 0x4000, SIS_AC97_SECONDARY  = 0x0080,
};
enum serial_intf_ctrl_bits {
	WARM_REST   = 0x00000001, COLD_RESET  = 0x00000002,
	I2S_CLOCK   = 0x00000004, PCM_SEC_AC97= 0x00000008,
	AC97_DBL_RATE = 0x00000010, SPDIF_EN  = 0x00000020,
	I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
	PCMIN       = 0x00000100, LINE1IN     = 0x00000200,
	MICIN       = 0x00000400, LINE2IN     = 0x00000800,
	HEAD_SET_IN = 0x00001000, GPIOIN      = 0x00002000,
	/* 7018 spec says id = 01 but the demo board routed to 10
	   SECONDARY_ID= 0x00004000, */
	SECONDARY_ID= 0x00004000,
	PCMOUT      = 0x00010000, SURROUT     = 0x00020000,
	CENTEROUT   = 0x00040000, LFEOUT      = 0x00080000,
	LINE1OUT    = 0x00100000, LINE2OUT    = 0x00200000,
	GPIOOUT     = 0x00400000,
	SI_AC97_PRIMARY_READY   = 0x01000000,
	SI_AC97_SECONDARY_READY = 0x02000000,
};

enum global_control_bits {
	CHANNLE_IDX = 0x0000003f, PB_RESET    = 0x00000100,
	PAUSE_ENG   = 0x00000200,
	OVERRUN_IE  = 0x00000400, UNDERRUN_IE = 0x00000800,
	ENDLP_IE    = 0x00001000, MIDLP_IE    = 0x00002000,
	ETOG_IE     = 0x00004000,
	EDROP_IE    = 0x00008000, BANK_B_EN   = 0x00010000
};

enum channel_control_bits {
	CHANNEL_LOOP   = 0x00001000, CHANNEL_SIGNED = 0x00002000,
	CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
};

enum channel_attribute {
	/* playback/record select */
	CHANNEL_PB     = 0x0000, CHANNEL_SPC_PB = 0x4000,
	CHANNEL_REC    = 0x8000, CHANNEL_REC_PB = 0xc000,
	/* playback destination/record source select */
	MODEM_LINE1    = 0x0000, MODEM_LINE2    = 0x0400,
	PCM_LR         = 0x0800, HSET           = 0x0c00,
	I2S_LR         = 0x1000, CENTER_LFE     = 0x1400,
	SURR_LR        = 0x1800, SPDIF_LR       = 0x1c00,
	MIC            = 0x1400,
	/* mist stuff */
	MONO_LEFT      = 0x0000, MONO_RIGHT     = 0x0100,
	MONO_MIX       = 0x0200, SRC_ENABLE     = 0x0080,
};

//7019
#define SiS7019_GLOBAL_CONTROL  0x0
#define SiS7019_SOFTWARE_RST    0x1

#define SiS7019_GLOBAL_INT_EN   0x04
#define SiS7019_ATIMER_INT_EN   0x8
#define SiS7019_AREC_INT_EN   0x4
#define SiS7019_APB_INT_EN   0x2
#define SiS7019_AWE_INT_EN   0x1

#define SiS7019_GLOBAL_INT_STS  0x08
#define SiS7019_ATIMER_INT      0x8

#define SiS7019_GLOBAL_TIMER    0x0C
#define SiS7019_ATIMER_EN       0x8000

#define SiS7019_PLAYBACK_START_A 0x14
#define SiS7019_PLAYBACK_START_B 0x18
#define SiS7019_PLAYBACK_STOP_A  0x1C
#define SiS7019_PLAYBACK_STOP_B  0x20
#define SiS7019_RECORD_START     0x24
#define SiS7019_RECORD_STOP      0x28
#define SiS7019_PLAYBACK_INT_A   0x2C
#define SiS7019_PLAYBACK_INT_B   0x30
#define SiS7019_RECORD_INT       0x34

#define SiS7019_ACLINK_PLAY_SOURCE  0x40
#define SiS7019_SPDIF_PLAY_SOURCE   0x44

#define SiS7019_ACLINK_COMMAND  0x50
#define SiS7019_ACLINK_SEMAPHORE   0x54
#define SiS7019_ACLINK_STATUS    0x58
#define SiS7019_AUDIO_ALIVE      0x1000
#define SiS7019_MODEM_ALIVE      0x2000
#define SiS7019_PRI_CODEC_RDY    0x100
#define SiS7019_CODEC_COLD_RESET  0x4
#define SiS7019_CODEC_WARM_RESET  0x5
#define SiS7019_PRI_CODEC_WR      0x8
#define SiS7019_PRI_CODEC_RD      0x9
#define SiS7019_SECOND_CODEC_WR   0xa
#define SiS7019_SECOND_CODEC_RD   0xb
#define SiS7019_THIRD_CODEC_WR    0xc
#define SiS7019_THIRD_CODEC_RD    0xd

#define SiS7019_COMMAND_WAIT     0x1
#define SiS7019_AUDIO_ALIVE_SET  0x80000000
#define SiS7019_PB_MAIN_EN       0x10000
#define SiS7019_REC_MIC_EN       0x2000
#define SiS7019_REC_PCM_EN       0x1000
#define SiS7019_ACLINK_AUDIO_CFG 0x5C
#define SiS7019_MODEM_ALIVE_SET  0x80000000
#define SiS7019_ACLINK_MODEM_CFG 0x60
#define SiS7019_SPDIF_OUT_ENABLE 0x1
#define SiS7019_SPDIF_CONFIG     0x74

#define SiS7019_PB_INT_STS_A     0x2C
#define SiS7019_PB_INT_STS_B     0x30
#define SiS7019_REC_INT_STS      0x34
#define SiS7019_PAUSE_ENGINE     0x1

#define SiS7019_PB_SYNC_A        0x80
#define SiS7019_PB_SYNC_B        0x84
#define SiS7019_PB_SYNC_C        0x88
#define SiS7019_PB_SYNC_D        0x8C
#define SiS7019_MX_SYNC          0x90

#define SiS7019_WE_CONTROL       0xA0
#define SiS7019_ENV_INT_STS_A    0xA8
#define SiS7019_ENV_INT_STS_B    0xAC

// channel register
#define SIS_TXBM_PRAM_A                  0x00
#define SIS_TXBM_PRAM_B                  0x04
#define SIS_TXBM_PRAM_C                  0x08
#define SIS_TXBM_PRAM_D                  0x0c      //most complicate

//new spec
#define TXPRAM_OFFSET     0x0
#define RXPRAM_OFFSET     0x800
#define WEPRAM_OFFSET     0x2000
#define DLINK_OFFSET      0x1000
#define DLIST_OFFSET      0x1400

#define SIS_RXBM_PRAM_A                  0x800
#define SIS_RXBM_PRAM_B                  0x804
#define SIS_RXBM_PRAM_C                  0x808
#define SIS_WE_GENERAL_PARAMETERS        0x2000
#define SIS_WE_GENERAL_PARAMETERS_AS     0x2004
#define SIS_WE_ARTICULATION_SCALES       0x2008
#define SIS_WE_TIMER_SET                 0x200C
#define SIS_WE_GENERATOR_VALUE           0x2010
#define SIS_WE_CHANNEL_CONTROL_LFO       0x2014
#define SIS_WE_LFO_EG_A                  0x2018
#define SIS_WE_LFO_EG_B                  0x201C
#define SIS_WE_LFO_EG_C                  0x2020
#define SIS_WE_LFO_EG_D                  0x2024
#define SIS_DESTINATION_LINK             0x1000
#define SIS_DESTINATION_LIST             0x1400

#define SIS_ESO_INT_EN		         0x40000
#define SIS_MLP_INT_EN		         0x10000
#define SIS_ELP_INT_EN                   0x20000
#define SIS_RELEASE_EN			 0x2000000
#define SIS_LOOP_EN                      0x1000000

#define SIS7019_BANK_A			0
#define SIS7019_BANK_C			1
//7019 end

#define TRID_REG( sis7019, x ) ( (sis7019) -> iobase + (x) )

#define VALIDATE_MAGIC(FOO,MAG)				\
({						  \
	if (!(FOO) || (FOO)->magic != MAG) { \
		printk(invalid_magic,__FUNCTION__);	       \
		return -ENXIO;			  \
	}					  \
})

#define VALIDATE_STATE(a) VALIDATE_MAGIC(a,sis7019_STATE_MAGIC)
#define VALIDATE_CARD(a) VALIDATE_MAGIC(a,sis7019_CARD_MAGIC)

extern __inline__ unsigned ld2(unsigned int x)
{
	unsigned r = 0;

	if (x >= 0x10000) {
		x >>= 16;
		r += 16;
	}
	if (x >= 0x100) {
		x >>= 8;
		r += 8;
	}
	if (x >= 0x10) {
		x >>= 4;
		r += 4;
	}
	if (x >= 4) {
		x >>= 2;
		r += 2;
	}
	if (x >= 2)
		r++;
	return r;
}

#endif /* __SIS7019_H */